This invention relates to programmable logic array integrated circuit devices, and more particularly to the manner in which such devices are organized.
Programmable logic array integrated circuit devices are well known, as is shown, for example, by Cliff et al. U.S. Pat. No. 5,260,611 and Cliff et al. U.S. Pat. No. 5,689,195, both of which are hereby incorporated by reference herein. Typical devices of these general kinds include a plurality of regions of programmable logic, each region being programmable to perform any of a plurality of relatively elementary logic functions on input signals applied to the region. A network of interconnection conductors is also provided on the device for programmably conveying signals to, from, and between the logic regions. By interconnecting the logic regions in various ways, the elementary logic functions performed by the individual regions can be concatenated to perform very complex logic.
The basic logic of the logic regions may be look-up table logic (as is discussed for the most part in the two references mentioned above), product term type logic (as is discussed for the most part in Wong et al. U.S. Pat. No. 4,871,930 (which is also hereby incorporated by reference herein)), or any other suitable type of logic. Any of these technologies may be used in the devices of this invention.
Programmable logic devices are usually intended as general-purpose devices. The designer of the device therefore does not know how much circuitry to provide for interconnecting the logic regions of the device. Some users may require large amounts of interconnection resources, while other users may require smaller amounts of such resources. Although it is theoretically possible to provide completely universal interconnection resources (which would allow any connection to be made no matter what other connections were also required), that is generally regarded as wasteful because only a small fraction of such completely universal interconnection resources are ever likely to be used. Thus one of the problems that the designer of programmable logic devices must deal with is to devise interconnection resources that are sufficient to meet the needs of most probable applications of the device without being wastefully more than will generally be needed. It is also important to avoid requirements for passing signals through large numbers of interconnection elements because such elements tend to slow down signal transmission and therefore reduce the operating speed of the device.
In view of the foregoing, it is an object of this invention to provide improved interconnection resources for programmable logic array integrated circuit devices.
It is a more particular object of the invention to provide interconnection resources for programmable logic array integrated circuit devices that provide a high degree of interconnection flexibility at relatively low cost in terms of xe2x80x9coverheadxe2x80x9d such as space occupied by interconnection conductors, programmable interconnections and the programmable elements required to control them, etc.
These and other objects of the invention are accomplished in accordance with the principles of the invention by grouping region output signals in groups of such signals, each of which groups has associated drivers for selectively applying signals to interconnection conductors of the device. Each driver can output any of the associated region output signals. This sharing of several drivers by several region output signals conserves driver resources and increases output signal routing flexibility.
The regions are disposed on the device in a two-dimensional array of intersecting rows and columns of regions. Horizontal interconnection conductors are associated with and extend along each row of regions. Vertical interconnection conductors are associated with and extend along each column of regions. Region-feeding conductors are provided for bringing signals into each region. Direct programmable connections are provided from both the horizontal and vertical conductors adjacent to a region to the region-feeding conductors associated with that region to avoid the need to route signals from a vertical conductor, for example, to a horizontal conductor and then to a region-feeding conductor.
Vertical conductors may be segmented and provided with programmable interconnections between the segments so that each segment can be used separately to provide a relatively short interconnection, or so that two (or more) segments can be interconnected to provide one relatively long interconnection.
If the device has only a relatively small number of rows, each region output in each column may have its own dedicated vertical conductor, thereby eliminating the need for tri-state driving of the vertical conductors.
In a device with a column of random access memory (xe2x80x9cRAMxe2x80x9d) usable by the user of the device (in addition to the previously described columns of programmable logic regions), greater use may be made of the vertical conductors associated with the RAM column by connecting those vertical conductors to the horizontal conductors of the device in such a way as to render the RAM column vertical conductors usable as alternate paths for transmitting signals between the rows of the device.
To simplify the structure for routing signals to input/output (xe2x80x9cI/Oxe2x80x9d) cells of the device, each I/O cell may always be driven directly by a particular subregion of a particular region. This may also allow the structure of the I/O cells to be simplified by performing some I/O cell functions in the associated subregions.
An additional function for the region-feeding conductors may be to make programmable connections between various segments of segmented horizontal conductors.
To facilitate use of subregions for both combinatorial logic and to perform a separate xe2x80x9clonely-registerxe2x80x9d function, both a combinatorial output and a registered output of each subregion may be connectable to conductors which can provide local or global interconnections.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.